Sur la Vérification de la Satisfaction pour la Logique des Différences

In this thesis, we develop a mixed SAT solver for differencelogic (DL) to carry out bounded model checking for timed systems. We defineDL as an extension of propositional Boolean logic with difference constraintsof the form (x-y¡c). We present algorithms to convert formulae in this logic tothe mixed conjunctive normal form, which is appropriate for solving purposes.We examine the architecture of existing Boolean SAT solvers and the techniquesthey use. Some of them are extended and integrated in the mixed solver alongwith newly developed methods specific to difference constraints.We focus on three classes of timed systems, namely timed automata, asyn-chronous digital circuits, and non-preemptive job-shops, and explain how theycan be expressed in DL. Problems belonging to these classes are generated toevaluate the performance of an experimental implementation of a mixed SATsolver.